The trend toward smaller sizes, lighter weights and increased capabilities in electrical equipment has brought a shift in the dominant semiconductor mounting process from pin insertion to surface mounting. Progress of semiconductor devices toward a higher degree of integration entails the enlargement of dies to a size as large as 10 mm or more per side. For semiconductor devices using such large size dies, greater stresses are applied to the die and the encapsulant during solder reflow. Such stresses are problematic because separation occurs at the interface between the encapsulant and the die or substrate, and the package cracks upon substrate mounting.
From the expectation that the use of leaded solders will be banned in the near future, a number of lead-substitute solders have been developed. Since most substitute solders have a higher melting temperature than the leaded solders, it has been considered to carry out reflow at temperatures of 260 to 270° C. At higher reflow temperatures, more failures are expected with encapsulants of prior art liquid epoxy resin compositions. Even with flip chip type packages which have raised no substantial problems in the prior art, the reflow at such high temperatures brings about serious problems that cracks can occur during the reflow and the encapsulant can peel at interfaces with chips or substrates. Also undesirably, cracks can occur in the resin, substrate, chip and bumps after several hundreds of thermal cycles.
Also the progress toward higher integration raises a problem of hindered infiltration. In the case of semiconductor using lead wires, as the pitch between leads becomes narrower, the resin is prevented from infiltrating therebetween. In flip-chip semiconductor devices, the infiltration ability is worsened as the pitch between bumps becomes narrower.